|
全国报名免费热线：4008699035 微信：shuhaipeixun
或15921673576（微信同号） QQ:1299983702 |
|
 Virtuoso UltraSim Full-chip Simulator vMMSIM培训 |
| 入.学.要.求 |
|
学员学习本课程应具备下列基础知识：
◆ 电路系统的基本概念。 |
|
班.级.规.模.及.环.境--热.线:4008699035 手.机:15921673576( 微.信.同.号) |
|
坚持小班授课，为保证培训效果，增加互动环节，每期人数限3到5人。 |
|
上.课.时.间.和.地.点 |
上课地点：【上海】：同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】：电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】：北京中山学院/福鑫大楼 【南京分部】：金港大厦(和燕路) 【武汉分部】：佳源大厦（高新二路） 【成都分部】：领馆区1号（中和大道） 【沈阳分部】：沈阳理工大学/六宅臻品 【郑州分部】：郑州大学/锦华大厦 【石家庄分部】：河北科技大学/瑞景大厦 【广州分部】：广粮大厦 【西安分部】：协同大厦
最近开课时间(周末班/连续班/晚班）：Virtuoso UltraSim Full-chip Simulator vMMSIM培训：即将开课，详情请咨询客服！ |
|
实.验.设.备 |
☆资深工程师授课
☆注重质量
☆边讲边练
☆合格学员免费推荐工作
☆合格学员免费颁发相关工程师等资格证书，提升您的职业资质
专注高端培训15年，曙海提供的证书得到本行业的广泛认可，学员的能力
得到大家的认同，受到用人单位的广泛赞誉。
★实.验.设.备请点击这儿查看★ |
|
最.新.优.惠 |
|
◆在读学生，可优惠。 |
|
质.量.保.障 |
|
1、免费重修；
2、课程结束后,授课老师留联系方式,保障培训效果,免费技术支持。
3、推荐机会。 |
Virtuoso UltraSim Full-chip Simulator vMMSIM培训
|
Course Description
In this course, you run FastSPICE simulation on large, complex, mixed-signal designs using the Virtuoso? UltraSim Full-chip Simulator. You explore the capabilities, methods, and modes of the simulator. You apply a variety of configurations that exploit the simulator's commands and options. You gain experience with hierarchical simulations, simulations of individual blocks, aged simulations, and EMIR analysis.
Learning Objectives
After completing this course, you will be able to:
- Simulate complex mixed-signal circuits quickly, using the FastSPICE simulator and Virtuoso UltraSim Full-chip Simulator
- Adjust the simulator's option settings to produce the proper tradeoff between accuracy and speed
- Construct probes and measures for reporting circuit performance during simulation
- Examine postprocessing measurement
- Verify the circuit performance and identify the potential failure modes by running advanced analysis, including static and dynamic checks
- Run hierarchical top-level simulations for prelayout, combining transistor-level schematics with structural Verilog? HDL, behavioral Verilog-A models, or behavioral Verilog HDL models, digital stimulus (.vec, .vcd) files and postlayout simulation with adjustable parasitic reduction
- Analyze the potential IR drop and electromigration (EM) problems in the layout by using Power IR/EM option and netlist-based EMIR
- Effectively use the integration of FastSPICE simulation in the Analog Design Environment to improve silicon accuracy and time-to-market
|
|
|
首页 课程表 报名 在线聊 讲师 品牌 QQ聊 活动 就业
