北京上海成都西安Allegro FPGA System Planner培训成都常州济南长沙武汉重庆哪家好哪里有

全国报名免费热线：4008699035 微信：shuhaipeixun
或15921673576（微信同号） QQ:1299983702

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　　　Allegro FPGA System Planner培训

班.级.规.模.及.环.境--热.线:4008699035 手.机:15921673576( 微.信.同.号)

坚持小班授课，为保证培训效果，增加互动环节，每期人数限3到5人。

上.课.时.间.和.地.点

上课地点：【上海】：同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】：电影大厦(地铁一号线大剧院站)/深圳大学成教院【北京分部】：北京中山学院/福鑫大楼【南京分部】：金港大厦(和燕路) 【武汉分部】：佳源大厦（高新二路）【成都分部】：领馆区1号（中和大道）【沈阳分部】：沈阳理工大学/六宅臻品【郑州分部】：郑州大学/锦华大厦【石家庄分部】：河北科技大学/瑞景大厦【广州分部】：广粮大厦【西安分部】：协同大厦
最近开课时间(周末班/连续班/晚班）：Allegro FPGA System Planner培训：即将开课，详情请咨询客服！

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质.量.保.障

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　　Allegro FPGA System Planner培训

培训方式以讲课和实验穿插进行。

课程描述：

Category:?Front End

Course Description

In the Allegro? FPGA System Planner (FSP) course, you learn to define your FPGA system and synthesize the connections in your design. You generate a schematic and PCB Editor database, so the FPGA I/O assignments can be optimized in the board environment.

Learning Objectives

After completing this course, you will be able to:

Identify how data flows from the FPGA System Planner (FSP) to the schematic and PCB
Create a design in FSP
Define the protocols and interfaces in an FSP design
Synthesize the connections in FSP protocols and interfaces
Add terminations and external ports in an FSP design
Generate an Allegro Design Entry HDL schematic from your FSP design
Export your FSP placement to the PCB Editor
Back annotate pin swaps and design changes from the schematic and PCB Editor to FSP

Software Used in This Course

Allegro FPGA System Planner
Allegro Design Entry HDL

Software Release(s)

SPB 16.5

Course Agenda

Note that this course can be tailored to better meet your needs?–?contact the Cadence training staff?for specifics.

Day 1

FPGA System Creation
FPGA System Synthesis
FPGA System Completion

Day 2

Integration with Design Entry HDL and PCB Editor
Postlayout Optimization
Importing FPGA Constraint Files and Virtual Interfaces
FSP Models

Audience

Design Engineers
FPGA Designers
PCB Designers